The present invention relates to a bus state control circuit of a microprocessor, and particularly to a bus state control circuit provided within a microprocessor to which an input-output control (peripheral control) IC is coupled by a bus.
Access by a microprocessor to an input-output control IC, such as a communication control IC and a magnetic disk control IC, has been made heretofore by executing input-output instructions. Ordinarily there is no problem with the "time for recovery" of the input-output control IC, i.e. the period of time between the end of one access and the start of a subsequent access, even when the same input-output control IC is accessed successively according to predetermined instructions, since the operating frequency of the microprocessor is low and an instruction fetch operation to retrieve the next instruction invariably comes in between input-output accesses.
FIG. 1 is a timing chart relating to an external access in the case when a microprocessor successively executes input-output instructions in a conventional manner. A strobe signal DS is used for reading and writing data, and it signifies the time when access is possible. The "time for recovery" is seen as the period between the point in time when the strobe signal turns inactive and the point in time when it turns active again for accessing the new input-output control IC. As shown in FIG. 1, since the instruction fetch cycle is inserted between the subsequent input-output access cycles, a long recovery time is obtained, even if the same input-output control IC is successively accessed.
Along with improvements in the integration capability of LSI, the performance and function of microprocessors currently are approaching those of minicomputers and medium-sized general purpose computers. Improvements in the technologies for manufacturing microprocessor elements and the introduction of a pipeline structure in microprocessor architecture, has contributed to this advance.
With the improvement in microprocessor architecture, the ratio of external access, i.e., the so-called "bus access ratio", is increased to a very significant degree. In other words, processes such as instruction fetching, instruction decoding, operand access and instruction execution, which previously have been processed serially, now can be executed in parallel due to the pipeline structure of the microprocessor architecture. By the same token, as to operand access, the reading of an operand necessary for an instruction subsequent to a given instruction which is now being executed and the writing of an operand contained in an instruction which was already completed is successively required.
Also, as to input-output instructions, they are executed successively for the same input-output control IC, the input-output access cycles may sometime occur successively without insertion of the instruction fetch cycle. This causes a problem in that the time for recovery cannot be secured, because the period of time between the end of one access and the start of the subsequent access become short.
A system in which software is prepared so that input-output instructions may not be executed successively is one approach to solving the aforesaid problem. Such system, however, must consider factors relating to hardware such as the pipeline structure of a given microprocessor, the degree of parallel execution of instructions, the clock frequency and the time for recovery of the input-output control IC. Consequently, there is a significant burden placed on a software developer. Moreover, even if a program solution is devised, the same program may not operate in another system which has different factors relating to hardware. Furthermore, even if the software allows a sufficient time to be taken between input-output instructions, so that it may operate in various systems, it will not efficiently operate systems which do not require much time for recovery.
As described above, there are many shortcomings in the system in which the time for recovery is secured by software.
Another solution may be found in a system in which hardware provides a fixed time period for securing the time for recovery that always is inserted between accesses made for input and output. This system has a shortcoming in that an unnecessary amount of time is needed when accesses for input and output are not successively made to the same IC. This results in a limitation on system performance.